The present invention relates to an information processing device and a debugging technique for use therein, and relates to a technique that is effective for, e.g., microcomputers.
In respect to debugging of a computer system configured with multiple CPUs, a technique for ensuring exact synchronization in cooperative operation of breaks and step executions of the CPUs and observing temporal relations of output times of trace data obtained by tracing these CPUs is suggested in Patent Document 1. According to this technique, cooperation between or among the breaks of the CPUs is realized by hardware and exact synchronization of the breaks and step executions is accomplished. A cooperative debugging circuit is equipped with a combination circuit for break cooperation, a cooperative break control register, a cooperative break status register, a trace data storage unit, and an external device interface unit. The combination circuit for break cooperation combines break output signals from each CPU and generates a break input signal to the CPU. The trace data storage unit stores trace data obtained from the CPUs in association with trace data output time information.
A debugging device by which sequential order in time of occurrences of events recorded in a plurality of trace memories can be known irrespective of occurrence frequency by addition of fewer hardware elements is suggested in Patent Document 2. According to this device, when two sets of trace data obtained by tracing two CPUs are written into two respective trace memories, the temporal order of the occurrences of data stored in one trace memory and of data stored in the other trace memory is determined by writing into each trace memory a trace memory address of the other together with the trace data.